1. Field of the Invention
The present invention relates to a self-calibration circuit for capacitors. More particularly, the present invention relates to a self-calibration circuit for capacitors capable of reducing a calibration error caused by a reference voltage error.
2. Description of Related Art
A successive approximation type analog to digital converter (ADC) generally has an accurate resistor array or capacitor array, and the resistors or capacitors are generally arranged based on a binary-weighted approach. Taking the capacitors as an example, besides the capacitor of the most significant bit, a capacitance of each capacitor is a half of the capacitance of another capacitor in a descending order, so as to form a binary-weighted capacitor array. If the capacitance is inaccurate, a dynamical non-linearity error of the ADC is increased accordingly, which may lead to conversion errors between analog signals and digital signals.
During the fabrication process of an integrated circuit, an accuracy of a capacitor can only reach about 10 bits, and if the accuracy is required to be improved, a general method thereof is to modify the capacitor error to the minimum through multiple fabrication processes, or to calibrate the capacitance of the capacitor by laser trimming. However, such methods are expensive and time-consuming.
Therefore, in the related art, a self-calibration method is applied for calibrating the capacitor array, by which compensation capacitors corresponding to individual capacitor error are set in the capacitor array, and then the capacitances are compared according to a reference voltage and a reference capacitor, so as to determine the capacitance to be compensated. However, during the calibration process, if the reference voltage is inaccurate or has excessive noise, the calibration error is occurred, and the dynamical non-linearity error of the ADC is enlarged.